1. Field of the Invention
Embodiments of the present invention generally relate to a method and improved film stacks for contact plug or gate electrode used in semiconductor applications.
2. Description of the Related Art
Tungsten-containing films are typically used in multiple applications for semiconductor device fabrication. For example, metallic tungsten (W) has been a primary conductor for contacts and vias. Metallic tungsten is also used in bit lines. The typical film stack currently in use is Ti/TiN nucleation/CVD-W bulk, with the titanium (Ti)/titanium nitride (TiN) layers acting as liner or barrier films.
While titanium tetrachloride (TiCl4)-based TiN processes provide improved step coverage, the deposition is usually performed at temperatures much greater than 400° C., which is incompatible with many device integration processes. Meanwhile, various issues arise with depositing and using TiN films, especially as feature sizes decrease. One problem with TiN is that TiN has poor diffusion resistance, so that halide elements such as Cl (in CVD-TiN with TiCl4) and F (in CVD-W bulk with WF6) may diffuse into the device during subsequent thermal processing, thereby adversely increasing resistivity of the film and cause interface issues. In addition, as circuit densities increase, the widths of vias, contacts and other features have been decreased to sub-micron dimensions less than 40 nm or 30 nm, leaving limited or no space for low resistance CVD W bulk since the feature is already filled with CVD-TiN and high resistive CVD W nucleation layer. However, in the conventional TiN liner/barrier approach, CVD W bulk film does not grow on CVD-TiN unless a nucleation layer is deposited thereon first as a growth site for W bulk film.
Furthermore, as the barrier layers and liner layers formed in the interconnection line are typically formed on a dielectric layer, poor adhesion of the barrier layer and liner layers to the dielectric layer may result in film peeling and high contact resistivity, thereby adversely resulting in device failure and poor electrical performance.
Therefore, there is a need in various device integration processes for an improved integrated film stack with good barrier properties and reduced film stack resistivity while providing more room for subsequent low resistance gate metallization process.